(1) Field of the Invention
The present invention relates to the testing and debugging of electrical components. Specifically the present invention relates to the testing of memory cell arrays in the context of testing systems built with these arrays.
(2) Art Background
Once an electrical device or chip is built, it is necessary to test it to ensure that the chip operates correctly. Subsequent testing is often desired after the chip has been connected to other chips and/or mounted on a circuit board and placed within a system in order to ensure the correct operation of the system. Debugging may be required if the chip does not operate correctly. Debugging may also be required after the system has been operational for some time if subsequent errors arise during the operation of the system. Examples of desirable debugging aids include the ability to stop the operation of the system at any time, examine its entire "state"(the set of values held in memory elements), without affecting that state, and resume operation. The ability to modify the system's state and resume operation with the modified state is also highly desirable.
As the amount of logic and/or memory increases per chip, the ability to test and debug the chips becomes more difficult. In addition, as chip integration increases, state within the chip which needs to be accessible for debugging or testing purposes is not available directly at the pins of the chip package, while the higher integration level and complexity of the chip makes observation and control of the chip's internal state more and more important.
In addition to growing logic complexity, memory arrays are also being incorporated into chip designs. Memory elements are typically used either individually or in small groups (respectively, flipflops or registers), or in larger arrays. Large memory arrays have certain advantages when implemented as "self-timed" circuits, including lower power dissipation and area usage for a given level of performance, and simplified interconnection and verification with the rest of the logic on the chip. However, a traditional implementation of self-timed memory arrays reduces the amount of control over and observability of the contents of the memory arrays in the context of testing and debug. Thus a method whereby control and observability of the memory arrays to enable the debug capabilities described above is required.
The JTAG specification outlines a standard test interface, or port, and a JTAG port controller specification. A chip which complies with the JTAG specification is provided with at least four pins that receive a scan input, drive a scan output, and control the "mode"(whether and how the chip responds to input at its JTAG pins), and a JTAG clock to provide timing signals.
In the implementation described herein, for example, in one JTAG state ("shift-DR" state), the "scannable" state of the chip is both readable and writable as a single shift register connected from the JTAG scan input pin to the JTAG scan output pin. In this JTAG state, chip state information is serially input to the component to be tested through the scan input pin, or serially read at the scan output pin, or a combination of both. Once the state information is input, the component can be clocked in its normal (non-JTAG) mode to perform the debugging operation scanned in serially through the scan input pin. For additional information regarding the JTAG specification, see IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Std. 1149.1 (1990).
Certain problems arise in extending the debugging capabilities described above to include memory arrays. The additional logic required to connect all memory array elements into a single shift register is prohibitive both due to additional area usage and performance degradation. In addition, a self-timed memory array typically receives a single external clock, from which all other internal timing signals required for operation of the array are derived via delay circuits, logic gating, etc. A traditional implementation does not distinguish debug mode from normal operation mode, and as the state of the chip is being scanned in or out in the JTAG shift-DR state, the clock required for the shift operation will also trigger memory array operations, some of which, such as write or clear, may cause unplanned and undesired modification of the internal contents of the memory array. This would prevent the desired resumption of normal operation of the chip after the shift operation has concluded. Therefore, debugging capabilities for memory arrays are typically implemented by providing separate pins or ports through which the array elements or cells can be directly accessed. When debugging through separate pins, the state of the address, control and data registers do not necessarily correspond to the state of the data in the array because the data in the array were updated through the separate pins bypassing the address, control and data registers. Thus, the registers and the array are not in the same temporal state.
The present invention provides a method and apparatus to control the clock input and control signals to the memory array to prevent execution of a state-modifying memory operation in shift mode, while allowing all scannable state to be shifted without restriction. When all shift data is scanned into the component, the memory array operation, if any, dictated by the state of the scannable memory elements of the chip must then be executed, without affecting the state of any other memory elements, including other locations in the same memory array, other memory arrays, and all scannable memory elements, in order to prevent the progression in state of the address/control information of the memory array as well as other memory elements located on the chip during testing such that the state held in all memory elements throughout the chip will be at the same temporal state. Therefore the memory arrays can be debugged using the scan chain to read and write data to and from specified addresses in the memory array.